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  <code caretStop="6" text="adc a,reg8" actualValue="adc a," tstates="4 or 7 (HL)" flags="S Z H C are affected as defined|P/V detects overflow|N is reset" opcode="10001[reg8]" size="1">reg8 and the carry flag are added to A.</code>
  <code caretStop="6" text="adc a,imm8" actualValue="adc a," tstates="7" flags="S Z H C are affected as defined|P/V detects overflow|N is reset" opcode="11001110 : [imm8]" size="2">The immediate value and the carry flag are added to A.</code>
  <code caretStop="7" text="adc a,(regindex + ofs8)" actualValue="adc a,( + )" tstates="19" flags="S Z H C are affected as defined|P/V detects overflow|N is reset" opcode="[regindex] : 10001110 : [ofs8]" size="3">The value pointed to by index register regindex plus   ofs8, and the carry flag, are added to A.</code>
  <code caretStop="7" text="adc hl,reg16" actualValue="adc hl," tstates="15" flags="S Z C are affected as defined|P/V detects overflow|H is set if there is a carry out of bit 11|N is reset" opcode="11101101 : 01[reg16]1010" size="2">The value of reg16 and the carry flag are added to   HL.</code>
  <code caretStop="6" text="add a,reg8" actualValue="add a," tstates="4 or 7 (HL)" flags="S Z H C are affected as defined|P/V detects overflow|N is cleared" opcode="10000[reg8]" size="1">Adds reg8 to A.</code>
  <code caretStop="6" text="add a,imm8" actualValue="add a," tstates="7" flags="S Z H C are affected as defined|P/V detects overflow|N is cleared" opcode="11000110 : [imm8]" size="2">The immediate value is added to A.</code>
  <code caretStop="7" text="add a,(regindex + ofs8)" actualValue="add a,( + )" tstates="19" flags="S Z H C are affected as defined|P/V detects overflow|N is cleared" opcode="[regindex] : 10000110 : [ofs8]" size="3">Adds the value of the memory location pointed to by   regindex plus ofs8 to A.</code>
  <code caretStop="7" text="add hl,reg16" actualValue="add hl," tstates="11" flags="S Z P/V are unaffected|C is affected as defined|H is set if there is a carry out of bit 11|N is reset" opcode="00[reg16]1001" size="1">The value of reg16 is added to HL.</code>
  <code caretStop="7" text="add ix,reg16" actualValue="add ix," tstates="15" flags="S Z P/V are unaffected|C is affected as defined|H is set if there is a carry out of bit 11|N is reset" opcode="11011101 : 00[reg16]1001" size="2">The value of reg16 is added to IX.</code>
  <code caretStop="7" text="add iy,reg16" actualValue="add iy," tstates="15" flags="S Z P/V are unaffected|C is affected as defined|H is set if there is a carry out of bit 11|N is reset" opcode="11111101 : 00[reg16]1001" size="2">The value of reg16 is added to IY.</code>
  <code caretStop="3" text="cp reg8" actualValue="cp " tstates="4 or 7 (HL)" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="10111[reg8]" size="1">Subtracts reg8 from A and affects flags   according to the result. A is not modified.</code>
  <code caretStop="3" text="cp imm8" actualValue="cp " tstates="7" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="11111110 : [imm8]" size="2">Subtracts the immediate value from A and affects flags according to   the result. A is not modified.</code>
  <code caretStop="4" text="cp (regindex + ofs8)" actualValue="cp ( + )" tstates="19" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="[regindex] : 10111110 : [ofs8]" size="3">Subtracts the memory value pointed to by regindex plus   ofs8 from A and affects the flags according to the   result. A is not modified.</code>
  <code caretStop="2" text="cpd" actualValue="cpd" tstates="16" flags="S Z H are affected as defined|P/V is reset if BC becomes zero|N is set|C is unaffected" opcode="11101101 : 10101001" size="2">Compares the value of the memory location pointed to by HL with   A. HL and BC are then decremented.</code>
  <code caretStop="3" text="cpdr" actualValue="cpdr" tstates="If BC != 0 and Z is reset: 21|  If BC == 0 or Z is set: 16" flags="S Z H are affected as defined|P/V is reset if BC becomes zero|N is set|C is unaffected" opcode="11101101 : 10111001" size="2">Compares the value of the memory location pointed to by HL with   A. HL and BC are then decremented. If BC is   not zero and Z is not set, this operation is repeated. Interrupts can   trigger while this instruction is processing.</code>
  <code caretStop="2" text="cpi" actualValue="cpi" tstates="16" flags="S Z H are affected as defined|P/V is reset if BC becomes zero|N is set|C is unaffected" opcode="11101101 : 10100001" size="2">Compares the value of the memory location pointed to by HL with   A. HL is incremented and BC is decremented.</code>
  <code caretStop="3" text="cpir" actualValue="cpir" tstates="If BC != 0 and Z is reset: 21|  If BC == 0 or Z is set: 16" flags="S Z H are affected as defined|P/V is reset if BC becomes zero|N is set|C is unaffected" opcode="11101101 : 10110001" size="2">Compares the value of the memory location pointed to by HL with   A. HL is incremented and BC is decremented. If   BC is not zero and Z is not set, this operation is repeated.   Interrupts can trigger while this instruction is processing.</code>
  <code caretStop="2" text="cpl" actualValue="cpl" tstates="4" flags="S Z P/V C are not affected|H N are set" opcode="00101111" size="1">The contents of A are inverted (one's complement).</code>
  <code caretStop="2" text="daa" actualValue="daa" tstates="4" flags="S Z are affected as defined|P/V is parity|N is unaffected|See instruction for H C" opcode="00100111" size="1">Adjusts A for BCD addition and subtraction operations.</code>
  <code caretStop="4" text="dec reg8" actualValue="dec " tstates="4 or 11 (HL)" flags="S Z H are affected as defined|P/V is set if operand was $80 before operation|N is set|C is unaffected" opcode="00[reg8]101" size="1">Subtracts one from reg8.</code>
  <code caretStop="5" text="dec (regindex + ofs8)" actualValue="dec ( + )" tstates="23" flags="S Z H are affected as defined|P/V is set is operand was $80 before operation|N is set|C is unaffected" opcode="[regindex] : 00110101 : [ofs8]" size="3">Subtracts one from the memory location pointed to by   regindex plus ofs8.</code>
  <code caretStop="4" text="dec reg16" actualValue="dec " tstates="6" opcode="00[reg16]1011" size="1">Subtracts one from reg16.</code>
  <code caretStop="4" text="dec regindex" actualValue="dec " tstates="10" opcode="[regindex] : 00101011" size="2">Subtracts one from regindex.</code>
  <code caretStop="4" text="inc reg8" actualValue="inc " tstates="4 or 11 (HL)" flags="S Z H are affected as defined|P/V is set is operand was $7F before operation|C is unaffected" opcode="00[reg8]100" size="1">Adds one to reg8.</code>
  <code caretStop="5" text="inc (regindex + ofs8)" actualValue="inc ( + )" tstates="23" flags="S Z H are affected as defined|P/V is set is operand was $7F before operation|C is unaffected" opcode="[regindex] : 00110100 : [ofs8]" size="3">Adds one to the memory location pointed to by regindex   plus ofs8.</code>
  <code caretStop="4" text="inc reg16" actualValue="inc " tstates="6" opcode="00[reg16]0011" size="1">Adds one to reg16.</code>
  <code caretStop="4" text="inc regindex" actualValue="inc " tstates="10" opcode="[regindex] : 00100011" size="2">Adds one to regindex.</code>
  <code caretStop="2" text="neg" actualValue="neg" tstates="8" flags="S Z H are affected as defined|P/V is set if A was $80 before operation|N is set|C is set if A was not $00 before operation" opcode="11101101 : 01000100" size="2">The contents of A are negated (two's complement). Operation is the   same as subtracting A from zero.</code>
  <code caretStop="6" text="sbc a,reg8" actualValue="sbc a," tstates="4 or 7 (HL)" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="10011[reg8]" size="1">Subtracts reg8 and the carry flag from A.</code>
  <code caretStop="6" text="sbc a,imm8" actualValue="sbc a," tstates="7" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="11011110 : [imm8]" size="2">Subtracts the immediate value and the carry flag from A.</code>
  <code caretStop="7" text="sbc a,(regindex + ofs8)" actualValue="sbc a,( + )" tstates="19" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="[reg16] : 10011110 : [ofs8]" size="3">Subtracts the value at the memory location pointed to by   regindex plus ofs8, and the carry flag   from A</code>
  <code caretStop="7" text="sbc hl,reg16" actualValue="sbc hl," tstates="15" flags="S Z C are affected as defined|H is set if a borrow from bit 12|P/V detects overflow|N is set" opcode="11101101 : 01[reg16]0010" size="2">Subtracts reg16 and the carry flag from HL.</code>
  <code caretStop="6" text="sub a,reg8" actualValue="sub a," tstates="4 or 7 (HL)" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="10010[reg8]" size="1">Subtracts reg8 from A.</code>
  <code caretStop="6" text="sub a,imm8" actualValue="sub a," tstates="7" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="11010110 : [imm8]" size="2">Subtracts the immediate value from A.</code>
  <code caretStop="7" text="sub a,(regindex + ofs8)" actualValue="sub a,( + )" tstates="19" flags="S Z H C are affected as defined|P/V detects overflow|N is set" opcode="[reg16] : 10010110 : [ofs8]" size="3">Subtracts the value at the memory location pointed to by   regindex plus ofs8 from A</code>
  <code caretStop="4" text="and reg8" actualValue="and " tstates="4 or 7 (HL)" flags="S Z are affected as defined|H is set|P/V is parity|N C are reset" opcode="10100[reg8]" size="1">Bitwise AND on A with reg8.</code>
  <code caretStop="4" text="and imm8" actualValue="and " tstates="7" flags="S Z are affected as defined|H is set|P/V is parity|N C are reset" opcode="11100110 : [imm8]" size="2">Bitwise AND on A with imm8.</code>
  <code caretStop="5" text="and (regindex + ofs8)" actualValue="and ( + )" tstates="19" flags="S Z are affected as defined|H is set|P/V is parity|N C are reset" opcode="[regindex] : 10100110 [ofs8]" size="3">Bitwise AND on A with the data at the memory location pointed to by regindex plus ofs8.</code>
  <code caretStop="9" text="bit imm3,reg8" actualValue="bit ," tstates="8 or 12 (HL)" flags="S P/V are scrambled|Z is affected as defined|H is set|N is cleared|C is unaffected" opcode="11001011 : 01[imm3][reg8]" size="2">Tests bit imm3 of reg8.</code>
  <code caretStop="4" text="bit imm3,(regindex + ofs8)" actualValue="bit ,( + )" tstates="23" flags="S P/V are scrambled|Z is affected as defined|H is set|N is cleared|C is unaffected" opcode="[regindex] : 11001011 : [ofs8] :        01[imm3]110" size="4">Tests bit imm3 of the data at the memory location pointed to by regindex plus ofs8.</code>
  <code caretStop="0" text="ccf" actualValue="f" tstates="4" flags="S Z P/V are unaffected|H is the carry before operation|N is reset|See instruction for C" opcode="00111111" size="1">Inverts the value of the carry flag.</code>
  <code caretStop="3" text="or reg8" actualValue="or " tstates="4 or 7 (HL)" flags="S Z are affected as defined|P/V is parity|H N C are reset" opcode="10110[reg8]" size="1">Bitwise OR on A with reg8.</code>
  <code caretStop="3" text="or imm8" actualValue="or " tstates="7" flags="S Z are affected as defined|P/V is parity|H N C are reset" opcode="11110110 : [imm8]" size="2">Bitwise OR on A with imm8.</code>
  <code caretStop="4" text="or (regindex + ofs8)" actualValue="or ( + )" tstates="19" flags="S Z are affected as defined|P/V is parity|H N C are reset" opcode="[regindex] : 10110110 [ofs8]" size="3">Bitwise OR on A with the data at the memory location pointed to by regindex plus ofs8.</code>
  <code caretStop="9" text="res imm3,reg8" actualValue="res ," tstates="8 or 15 (HL)" opcode="11001011 : 10[imm3][reg8]" size="2">Resets bit imm3 of reg8.</code>
  <code caretStop="4" text="res imm3,(regindex + ofs8)" actualValue="res ,( + )" tstates="23" flags="Not affected" opcode="[regindex] : 11001011 : [ofs8] :      10[imm3]110" size="4">Resets bit imm3 of the value at the memory location pointed to by regindex plus ofs8.</code>
  <code caretStop="2" text="scf" actualValue="scf" tstates="4" flags="S Z P/V are unaffected|H N are reset|C is set" opcode="00110111" size="1">Sets the carry flag.</code>
  <code caretStop="9" text="set imm3,reg8" actualValue="set ," tstates="8 or 15 (HL)" opcode="11001011 : 11[imm3][reg8]" size="2">Sets bit imm3 of reg8.</code>
  <code caretStop="4" text="set imm3,(regindex + ofs8)" actualValue="set ,( + )" tstates="23" flags="Not affected" opcode="[regindex] : 11001011 : [ofs8] :      11[imm3]110" size="4">Sets bit imm3 of the value at the memory location pointed to by regindex plus ofs8.</code>
  <code caretStop="4" text="xor reg8" actualValue="xor " tstates="4 or 7 (HL)" flags="S Z are affected as defined|H is set|P/V is parity|N C are reset" opcode="10101[reg8]" size="1">Bitwise XOR on A with reg8.</code>
  <code caretStop="4" text="xor imm8" actualValue="xor " tstates="7" flags="S Z are affected as defined|H is set|P/V is parity|N C are reset" opcode="11101110 : [imm8]" size="2">Bitwise XOR on A with imm8.</code>
  <code caretStop="5" text="xor (regindex + ofs8)" actualValue="xor ( + )" tstates="19" flags="S Z are affected as defined|H is set|P/V is parity|N C are reset" opcode="[regindex] : 10101110 [ofs8]" size="3">Bitwise XOR on A with the data at the memory location pointed to by regindex plus ofs8.</code>
  <code caretStop="5" text="call imm16" actualValue="call " tstates="17" opcode="11001101 : immLSB : immMSB" size="2">The current PC value plus three is pushed onto the stack, then is loaded with imm16.</code>
  <code caretStop="8" text="call cc,imm16" actualValue="call ," tstates="If cc is true: 17|If cc is false: 10" opcode="11[cc]100 : immLSB : immMSB" size="2">If condition cc is true, the current PC value plus three is pushed onto the stack, then is loaded with imm16.</code>
  <code caretStop="5" text="djnz imm8" actualValue="djnz " tstates="If B is not 0: 13|If B is 0: 8" opcode="00010000 : [imm8]" size="2">The B register is decremented, and if not zero, the signed value imm8 is added to PC. The jump is measured from the address of the instruction op code.</code>
  <code caretStop="3" text="jp imm16" actualValue="jp " tstates="10" opcode="11000011 : [immLSB] : [immMSB]" size="3">imm16 is copied to PC.</code>
  <code caretStop="6" text="jp cc,imm16" actualValue="jp ," tstates="10" opcode="11[cc]010 : [immLSB] : [immMSB]" size="3">If condition cc is true, imm16 is copied to PC.</code>
  <code caretStop="3" text="jr imm8" actualValue="jr " tstates="12" opcode="00011000 : [imm8]" size="2">The signed value imm8 is added to PC. The jump is measured from the address of the instruction op code.</code>
  <code caretStop="6" text="jr cc,imm8" actualValue="jr ," tstates="If cc is true: 12|If cc is false: 7" opcode="001[cc]000" size="1">If condition cc is true, the signed value imm8 is added to PC. The jump is measured from the address of the instruction op code.</code>
  <code caretStop="2" text="nop" actualValue="nop" tstates="4" opcode="00000000" size="1">No operation is performed.</code>
  <code caretStop="2" text="ret" actualValue="ret" tstates="10" opcode="11001001" size="1">The top stack entry is popped into PC.</code>
  <code caretStop="4" text="ret cc" actualValue="ret " tstates="If cc is true: 11|If cc is false: 5" opcode="11[cc]000" size="1">If condition cc is true, the top stack entry is popped into PC.</code>
  <code caretStop="3" text="reti" actualValue="reti" tstates="14" opcode="11101101 : 01001101" size="2">Used at the end of a maskable interrupt service routine. The top stack entry is popped into PC, and signals an I/O device that the interrupt has finished, allowing nested interrupts (not a consideration on the TI).</code>
  <code caretStop="3" text="retn" actualValue="retn" tstates="14" opcode="11101101 : 01000101" size="2">Used at the end of a non-maskable interrupt service routine (located at $0066) to pop the top stack entry into PC. The value of IFF2 is copied to IFF1 so that maskable interrupts are allowed to continue as before. NMIs are not enabled on the TI.</code>
  <code caretStop="4" text="rst imm8" actualValue="rst " tstates="11" opcode="11[imm8]111" size="1">The current PC value plus three is pushed onto the stack. The MSB is loaded with $00 and the LSB is loaded with imm8.</code>
  <code caretStop="7" text="ex de,hl" actualValue="ex de,hl" tstates="4" opcode="11101011" size="1">Exchanges the 16-bit contents of DE and HL.</code>
  <code caretStop="8" text="ex af,af'" actualValue="ex af,af'" tstates="4" opcode="00001000" size="1">Exchanges the 16-bit contents of AF and AF'.</code>
  <code caretStop="9" text="ex (sp),hl" actualValue="ex (sp),hl" tstates="19" opcode="11100011" size="1">Exchanges (SP) with L, and (SP+1) with H.</code>
  <code caretStop="8" text="ex (sp),regindex" actualValue="ex (sp)," tstates="23" opcode="[regindex] : 11100011" size="2">Exchanges (SP) with the LSB of regindex, and (SP+1) with the MSB of regindex.</code>
  <code caretStop="2" text="exx" actualValue="exx" tstates="4" opcode="11011001" size="1">Exchanges the 16-bit contents of BC, DE, and HL with BC', DE', and HL'.</code>
  <code caretStop="3" text="ld reg8d,reg8s" actualValue="ld d,s" tstates="4 or 7 (HL)" opcode="01[reg8D][reg8S]" size="2">The contents of register reg8S are stored into reg8D.</code>
  <code caretStop="3" text="ld reg8,imm8" actualValue="ld ," tstates="7 or 10 (HL)" opcode="00[reg8]110 : [imm8]" size="2">Stores the immediate value into reg8.</code>
  <code caretStop="3" text="ld reg8,(regindex + ofs8)" actualValue="ld ,( + )" tstates="19" opcode="[regindex] : 01[reg8]110 : [ofs8]" size="3">Stores the value pointed to by regindex plus ofs8 into reg8.</code>
  <code caretStop="21" text="ld (regindex + ofs8),reg8" actualValue="ld ( + )," tstates="19" opcode="regindex : 01110[reg8] : [ofs8]" size="3">Stores reg8 into the memory location pointed to by regindex plus ofs8.</code>
  <code caretStop="23" text="ld (regindex + ofs8),  imm8" actualValue="ld ( + ),  " tstates="19" opcode="[regindex] : 00110110 : [ofs8] : [imm8]" size="4">Stores the immediate data into the memory location pointed to by regindex plus ofs8.</code>
  <code caretStop="6" text="ld a,(reg16)" actualValue="ld a,()" tstates="7" opcode="000[reg16]1010" size="1">Stores the value pointed to by reg16 into A.</code>
  <code caretStop="6" text="ld a,(imm16)" actualValue="ld a,()" tstates="13" opcode="00111010 : [immLSB] : [immMSB]" size="3">Stores the value pointed to by imm16 into A.</code>
  <code caretStop="4" text="ld (reg16),a" actualValue="ld (),a" tstates="7" opcode="000[reg16]0010">   Stores A into the memory location pointed to by   reg16.     Register  Bit Field       BC  0       DE  1    </code>
  <code caretStop="4" text="ld (imm16),a" actualValue="ld (),a" tstates="13" opcode="00110010 : [immLSB] : [immMSB]" size="3">Stores A into the memory location pointed to by imm16.</code>
  <code caretStop="13" text="ld a,{ i | r }" actualValue="ld a,{ i | r }" tstates="9" flags="S Z are affected as defined.|H N are reset.|P/V holds IFF2.|C is unaffected." opcode="11101101 : 0101[reg]111" size="2">Stores the value of register I or R into A</code>
  <code caretStop="13" text="ld { i | r },a" actualValue="ld { i | r },a" tstates="9" opcode="11101101 : 0100[reg]111" size="2">Stores the value of A into register I or R.</code>
  <code caretStop="3" text="ld reg16,imm16" actualValue="ld ," tstates="10" opcode="00[reg16]0001 : [immLSB] : [immMSB]" size="3">Stores the immediate data into register reg16.</code>
  <code caretStop="12" text="ld regindex,imm16" actualValue="ld ," tstates="14" opcode="[regindex] : 00100001 : [immLSB] :        [immMSB]" size="4">Loads the immediate data into index register regindex</code>
  <code caretStop="7" text="ld hl,(imm16)" actualValue="ld hl,()" tstates="16" opcode="00101010 : [immLSB] : [immMSB]" size="3">Loads the value pointed to by imm16 into HL.</code>
  <code caretStop="3" text="ld reg16,(imm16)" actualValue="ld ,()" tstates="20" opcode="11101101 : 01[reg16]1011 : [immLSB] :        [immMSB]" size="4">Loads the value pointed to by imm16 into register reg16.</code>
  <code caretStop="13" text="ld regindex,(imm16)" actualValue="ld ,()" tstates="20" opcode="[regindex] : 00101010 : [immLSB] :        [immMSB]" size="4">Loads the value pointed to by imm16 into index register regindex.</code>
  <code caretStop="4" text="ld (imm16),hl" actualValue="ld (),hl" tstates="16" opcode="00100010 : [immLSB] : [immMSB]" size="3">Stores the value of HL into the memory location pointed to by imm16.</code>
  <code caretStop="11" text="ld (imm16),reg16" actualValue="ld ()," tstates="20" opcode="11101101 : 01[reg16]0011 : [immLSB] :        [immMSB]" size="4">Stores the value of register reg16 into the memory location pointed to by imm16.</code>
  <code caretStop="4" text="ld (imm16),regindex" actualValue="ld ()," tstates="20" opcode="[regindex] : 00100010 : [immLSB] :        [immMSB]" size="4">Stores the value of index register regindex into the memory location pointed to by imm16.</code>
  <code caretStop="7" text="ld sp,hl" actualValue="ld sp,hl" tstates="6" opcode="11111001" size="1">Loads the value of HL into SP</code>
  <code caretStop="6" text="ld sp,regindex" actualValue="ld sp," tstates="10" opcode="[regindex] : 11111001" size="2">Loads the value of index register regindex into SP.</code>
  <code caretStop="2" text="ldd" actualValue="ldd" tstates="16" flags="S Z C are not affected|H N are reset|P/V is reset if BC becomes zero. Reset otherwise." opcode="11101101 : 10101000" size="2">Transfers a byte of data from the memory location pointed to by HL to the memory location pointed to by DE. Then HL, DE, and BC are decremented.</code>
  <code caretStop="3" text="lddr" actualValue="lddr" tstates="If BC != 0: 21|If BC == 0: 16" flags="S Z C are not affected|H N P/V are reset" opcode="11101101 : 10111000" size="2">Transfers a byte of data from the memory location pointed to by HL to the memory location pointed to by DE. Then HL, DE, and BC are decremented. If BC is not zero, this operation is repeated. Interrupts can trigger while this instruction is processing.</code>
  <code caretStop="2" text="ldi" actualValue="ldi" tstates="16" flags="S Z C are not affected|H N are reset|P/V is reset if BC becomes zero. Reset otherwise." opcode="11101101 : 10100000" size="2">Transfers a byte of data from the memory location pointed to by HL to the memory location pointed to by DE. Then HL and DE are incremented and BC is decremented.</code>
  <code caretStop="3" text="ldir" actualValue="ldir" tstates="If BC != 0: 21|If BC == 0: 16" flags="S Z C are not affected|H N P/V are reset" opcode="11101101 : 10110000" size="2">Transfers a byte of data from the memory location pointed to by HL to the memory location pointed to by DE. Then HL and DE are incremented and BC is decremented. If BC is not zero, this operation is repeated. Interrupts can trigger while this instruction is processing.</code>
  <code caretStop="4" text="pop reg16" actualValue="pop " tstates="10" opcode="11[reg16]0001" size="1">The memory location pointed to by SP is stored into regLSB and SP is incremented. The memory location pointed to by SP is stored into regMSB and SP is incremented again</code>
  <code caretStop="4" text="pop regindex" actualValue="pop " tstates="14" opcode="[regindex] : 11100001" size="2">The memory location pointed to by SP is stored into regLSB and SP is incremented. The memory location pointed to by SP is stored into regMSB and SP is incremented again</code>
  <code caretStop="5" text="push reg16" actualValue="push " tstates="11" opcode="11[reg16]0101" size="1">SP is decremented and regMSB is stored into the memory location pointed to by SP. SP is decremented again and regLSB is stored into the memory location pointed to by SP.</code>
  <code caretStop="5" text="push regindex" actualValue="push " tstates="15" opcode="[regindex] : 11100101" size="2">SP is decremented and regMSB is stored into the memory location pointed to by SP. SP is decremented again and regLSB is stored into the memory location pointed to by SP.</code>
  <code caretStop="1" text="di" actualValue="di" tstates="4" opcode="11110011" size="1">Resets both interrupt flip-flops, thus preventing maskable interrupts from triggering.</code>
  <code caretStop="1" text="ei" actualValue="ei" tstates="4" opcode="11111011" size="1">Sets both interrupt flip-flops, thus allowing maskable interrupts to occur. An interrupt will not occur until after the immediatedly following instruction.</code>
  <code caretStop="3" text="halt" actualValue="halt" tstates="4" opcode="01110110" size="1">Suspends CPU operation until an interrupt or reset occurs.</code>
  <code caretStop="3" text="im 0" actualValue="im 0" tstates="8" opcode="11101101 : 01000110" size="2">Sets interrupt mode 0.</code>
  <code caretStop="3" text="im 1" actualValue="im 1" tstates="8" opcode="11101101 : 01010110" size="2">Sets interrupt mode 1.</code>
  <code caretStop="3" text="im 2" actualValue="im 2" tstates="4" opcode="11101101 : 01011110" size="2">Sets interrupt mode 2.</code>
  <code caretStop="6" text="in a,(imm8)" actualValue="in a,()" tstates="11" opcode="11011011 : [imm8]" size="2">A byte from port imm8 is written to A.</code>
  <code caretStop="3" text="in reg8,(c)" actualValue="in ,(c)" tstates="12" flags="S Z are affected as defined|H N are reset|P/V is parity|C is not affected" opcode="11101011 : 01[reg8]000" size="2">A byte from port C is written to reg8.</code>
  <code caretStop="2" text="ind" actualValue="ind" tstates="16" flags="S H P/V are scrambled|Z is set if B becomes zero|N is set|C is not affected" opcode="11101101 : 10101010" size="2">A byte from port C is written to the memory location pointed to by HL. HL and B are then decremented.</code>
  <code caretStop="3" text="indr" actualValue="indr" tstates="If B != 0: 21|If B == 0: 16" flags="S H P/V are scrambled|Z N are set|C is not affected" opcode="11101101 : 10111010" size="2">A byte from port C is written to the memory location pointed to by HL. HL and B are then decremented. If B is not zero, this operation is repeated.</code>
  <code caretStop="2" text="ini" actualValue="ini" tstates="16" flags="S H P/V are scrambled|Z is set if B becomes zero|N is set|C is not affected" opcode="11101101 : 10100010" size="2">A byte from port C is written to the memory location pointed to by HL. HL is incremented and B is decremented.</code>
  <code caretStop="3" text="inir" actualValue="inir" tstates="If B != 0: 21|If B == 0: 16" flags="S H P/V are scrambled|Z N are set|C is not affected" opcode="11101101 : 10110010" size="2">A byte from port C is written to the memory location pointed to by HL. HL is incremented and B is decremented. If B is not zero, this operation is repeated.</code>
  <code caretStop="3" text="otdr" actualValue="otdr" tstates="If B != 0: 21|If B == 0: 16" flags="S H P/V are scrambled|Z N are set|C is not affected" opcode="11101101 : 10111011" size="2">A byte from the memory location pointed to by HL is written to port C. HL and B are then decremented. If B is not zero, this operation is repeated.</code>
  <code caretStop="3" text="otir" actualValue="otir" tstates="If B != 0: 21|If B == 0: 16" flags="S H P/V are scrambled|Z N are set|C is not affected" opcode="11101101 : 10110011" size="2">A byte from the memory location pointed to by HL is written to port C. HL is incremented and B is decremented. If B is not zero, this operation is repeated.</code>
  <code caretStop="5" text="out (imm8),a" actualValue="out (),a" tstates="11" opcode="11010011 : [imm8]" size="2">The value of A is written to port imm8.</code>
  <code caretStop="8" text="out (c),reg8" actualValue="out (c)," tstates="12" opcode="11101011 : 01[reg8]001" size="2">The value of reg8 is written to port C.</code>
  <code caretStop="3" text="outd" actualValue="outd" tstates="16" flags="S H P/V are scrambled|Z is set if B becomes zero|N is set|C is not affected" opcode="11101101 : 10101011" size="2">A byte from the memory location pointed to by HL is written to port C. HL and B are then decremented.</code>
  <code caretStop="3" text="outi" actualValue="outi" tstates="16" flags="S H P/V are scrambled|Z is set if B becomes zero|N is set|C is not affected" opcode="11101101 : 10100011" size="2">A byte from the memory location pointed to by HL is written to port C. HL is incremented and B is decremented.</code>
  <code caretStop="3" text="rl reg8" actualValue="rl " tstates="8 or 15 (HL)" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="11001011 : 00010[reg8]" size="2">The contents of reg8 are rotated left one bit position. The contents of bit 7 are copied to the carry flag and the previous contents of the carry flag are copied to bit 0.</code>
  <code caretStop="4" text="rl (regindex + ofs8)" actualValue="rl ( + )" tstates="23" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="[regindex] : 11001011 : [ofs8] : 00010110" size="4">The contents of the memory location pointed to by regindex plus ofs8 are rotated left one bit position. The contents of bit 7 are copied to the carry flag and the previous contents of the carry flag are copied to bit 0.</code>
  <code caretStop="2" text="rla" actualValue="rla" tstates="4" flags="S Z P/V are not affected|H N are reset|See instruction for C." opcode="00010111" size="1">The contents of A are rotated left one bit position. The contents of bit 7 are copied to the carry flag and the previous contents of the carry flag are copied to bit 0.</code>
  <code caretStop="4" text="rlc reg8" actualValue="rlc " tstates="8 or 15 (HL)" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="11001011 : 00000[reg8]" size="2">The contents of reg8 are rotated left one bit position. The contents of bit 7 are copied to the carry flag and bit 0.</code>
  <code caretStop="5" text="rlc (regindex + ofs8)" actualValue="rlc ( + )" tstates="23" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="[regindex] : 11001011 : [ofs8] : 00000110" size="4">The contents of the memory location pointed to by regindex plus ofs8 are rotated left one bit position. The contents of bit 7 are copied to the carry flag and bit 0.</code>
  <code caretStop="3" text="rlca" actualValue="rlca" tstates="4" flags="S Z P/V are not affected|H N are reset|See instruction for C." opcode="00000111" size="1">The contents of A are rotated left one bit position. The contents of bit 7 are copied to the carry flag and bit 0.</code>
  <code caretStop="2" text="rld" actualValue="rld" tstates="18" flags="Flags refer to state of A|S Z are affected as defined|H N is reset|P/V is parity|C is not affected" opcode="11101101 : 01101111" size="2">The contents of the low-order nibble of (HL) are copied to the high-order nibble of (HL). The previous contents are copied to the low-order nibble of A. The previous contents are copied to the low-order nibble of (HL).</code>
  <code caretStop="3" text="rr reg8" actualValue="rr " tstates="8 or 15 (HL)" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="11001011 : 00011[reg8]" size="2">The contents of reg8 are rotated right one bit position. The contents of bit 0 are copied to the carry flag and the previous contents of the carry flag are copied to bit 7.</code>
  <code caretStop="4" text="rr (regindex + ofs8)" actualValue="rr ( + )" tstates="23" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="[regindex] : 11001011 : [ofs8] : 00011110" size="4">The contents of the memory location pointed to by regindex plus ofs8 are rotated right one bit position. The contents of bit 0 are copied to the carry flag and the previous contents of the carry flag are copied to bit 7.</code>
  <code caretStop="2" text="rra" actualValue="rra" tstates="4" flags="S Z P/V are not affected|H N are reset|See instruction for C." opcode="00011111" size="1">The contents of A are rotated right one bit position. The contents of bit 0 are copied to the carry flag and the previous contents of the carry flag are copied to bit 7.</code>
  <code caretStop="4" text="rrc reg8" actualValue="rrc " tstates="8 or 15 (HL)" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="11001011 : 00001[reg8]" size="2">The contents of reg8 are rotated left one bit position. The contents of bit 0 are copied to the carry flag and bit 7.</code>
  <code caretStop="5" text="rrc (regindex + ofs8)" actualValue="rrc ( + )" tstates="23" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="[regindex] : 11001011 : [ofs8] : 00001110" size="4">The contents of the memory location pointed to by regindex plus ofs8 are rotated right one bit position. The contents of bit 0 are copied to the carry flag and bit 7.</code>
  <code caretStop="3" text="rrca" actualValue="rrca" tstates="4" flags="S Z P/V are not affected|H N are reset|See instruction for C." opcode="00001111" size="1">The contents of A are rotated right one bit position. The contents of bit 0 are copied to the carry flag and bit 7.</code>
  <code caretStop="2" text="rrd" actualValue="rrd" tstates="18" flags="Flags refer to state of A|S Z are affected as defined|H N is reset|P/V is parity|C is not affected" opcode="11101101 : 01100111" size="2">The contents of the low-order nibble of (HL) are copied to the low-order nibble of A. The previous contents are copied to the high-order nibble of (HL). The previous contents are copied to the low-order nibble of (HL).</code>
  <code caretStop="4" text="sla reg8" actualValue="sla " tstates="8 or 15 (HL)" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="11001011 : 00100[reg8]" size="2">The contents of reg8 are shifted left one bit position. The contents of bit 7 are copied to the carry flag and a zero is put into bit 0.</code>
  <code caretStop="5" text="sla (regindex + ofs8)" actualValue="sla ( + )" tstates="23" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="[regindex] : 11001011 : [ofs8] : 00100110" size="4">The contents of the memory location pointed to by regindex plus ofs8 are shifted left one bit position. The contents of bit 7 are copied to the carry flag and a zero is put into bit 0.</code>
  <code caretStop="4" text="sra reg8" actualValue="sra " tstates="8 or 15 (HL)" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="11001011 : 00101[reg8]" size="2">The contents of reg8 are shifted right one bit position. The contents of bit 0 are copied to the carry flag and the previous contents of bit 7 are unchanged.</code>
  <code caretStop="5" text="sra (regindex + ofs8)" actualValue="sra ( + )" tstates="23" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="[regindex] : 11001011 : [ofs8] : 00101110" size="4">The contents of the memory location pointed to by regindex plus ofs8 are shifted left one bit position. The contents of bit 7 are copied to the carry flag and a zero is put into bit 0.</code>
  <code caretStop="4" text="srl reg8" actualValue="srl " tstates="8 or 15 (HL)" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="11001011 : 00111[reg8]" size="2">The contents of reg8 are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.</code>
  <code caretStop="5" text="srl (regindex + ofs8)" actualValue="srl ( + )" tstates="23" flags="S Z are affected as defined|H N are reset|P/V is parity|See instruction for C" opcode="[regindex] : 11001011 : [ofs8] : 00111110" size="4">The contents of the memory location pointed to by regindex plus ofs8 are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.</code>
</CodeCompletion>